17、ogram Store Enable is the read strobe to external program memory When the AT89C51 is executing code from external program memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory EAVPPExternal Access Enable EA must be s 。

18、trapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFHNote however that if lock bit 1 is programmed EA will be internally latched on reset EA should be strapped to VCC for internal program executionsThis pin also receives the 1 。

19、2-volt programming enable voltage VPP during Flash programming for parts that require 12-volt VPPXTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit XTAL2Output from the inverting oscillator amplifierOscillator Characteristics XTAL1 and XTAL2 are the in 。

20、put and output respectivelyof an inverting amplifier which can be configured for use as an on-chip oscillator as shown in Figure 1 Either a quartz crystal or ceramic resonator may be used To drive the device from an external clock source XTAL2 should be left unconnected while XTAL1 is driven as show 。

21、n in Figure 2There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and imum voltage high and low time specifications must be observedIdle Mode In idle mode the CPU puts itself to sl 。

22、eep while all the on-chip peripherals remain active The mode is invoked by software The content of the on-chip RAM and all the special functions registers remain unchanged during this mode The idle mode can be terminated by any enabled interrupt or by a hardware reset It should be noted that when id 。

23、le is terminated by a hard ware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control On-chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To elimina 。

24、te the possibility of an unexpected write to a port pin when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memoryFigure 1 Oscillator ConnectionsNote C1 C2 30 pF 10 pF for Crystals 40 pF 10 pF for Ceramic Res 。

25、onatorsFigure 2 External Clock Drive ConfigurationPower-down Mode In the power-down mode the oscillator is stopped and the instruction that invokes power-down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated T 。

26、he only exit from power-down is a hardware reset Reset redefines the SFRs but does not change the on-chip RAM The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilizeProgram Memory Lock 。

27、 Bits On the chip are three lock bits which can be left unprogrammed U or can be programmed P to obtain the additional features listed in the table belowWhen lock bit 1 is programmed the logic level at the EA pin is sampled and latched during reset If the device is powered up without a reset the lat 。

28、ch initializes to a random value and holds that value until reset is activated It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properlyProgramming the Flash The AT89C51 is normally shipped with the on-chip Flas 。

29、h memory array in the erased state that is contents FFH and ready to be programmed The programming interface accepts either a high-voltage 12-volt or a low-voltage VCC program enable signal The low-voltage programming mode provides a convenient way to program the AT89C51 inside the users system whil 。

30、e the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmersThe AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled The respective top-side marking and device signature codes are listed in the following tableThe AT89C51 。

31、 code memory array is programmed byte-by-byte in either programming mode To program any non-blank byte in the on-chip Flash Memory the entire memory must be erased using the Chip Erase Mode Programming Algorithm Before programming the AT89C51 the address data and control signals should be set up acc 。

32、ording to the Flash programming mode table and Figures 3 and 4 To program the AT89C51 take the following steps1 Input the desired memory location on the address lines2 Input the appropriate data byte on the data lines 3 Activate the correct combination of control signals4 Raise EAVPP to 12V for the。

稿源：(未知)

【傻大方】网址：/a/2021/0813/0023654198.html

标题：AT89C51|AT89C51外文翻译毕业设计( 二 )